The present invention relates to a transmitting apparatus, a transmitting method, and a program storage medium, and more particularly to an apparatus for and a method of transmitting packets of data and a program storage medium.
When a transmitting apparatus for isochronously transmitting data via a bus based on the standards of IEEE (Institute of Electrical and Electronic Engineers) 1394 (hereinafter referred to as “1394 bus”) transmits MPEG (Moving Picture Experts Group) 2-TS (Transport Stream) data, a dedicated CPU (Central Processing Unit) monitors the cycle time of the 1394 bus to control the size of data to be transmitted.
Some personal computers are equipped with a 1394 interface. To meet demands for inexpensive 1394 interfaces, the 1394 interfaces do not have a dedicated CPU, and packets whose size has been controlled are transmitted to the 1394 bus by a general-purpose 1394 DMA (Direct Memory Access) controller.
FIG. 1 of the accompanying drawings is a block diagram showing a conventional transmitting apparatus for isochronously transmitting data via a 1394 bus by means of a 1394 DMA controller.
As shown in FIG. 1, a CPU 1 controls an IDE (Integrated Drive Electronics) controller 3 to read MPEG2-TS data (hereinafter also referred to as “TSP (Transport Stream Packet)”) from a storage device 2, and stores the read MPEG2-TS data together with a CIP (Common Isochronous Packet) and a SPH (Source Packet Header) as isochronous packets in a main memory 4.
The CPU 1 stores a description of a transmission pattern representing the arrangement of isochronous packets storing TSPs, in the main memory 4.
FIG. 2 of the accompanying drawings is a diagram showing isochronous packets transmitted from the transmitting apparatus. Isochronous packets that are isochronously transmitted on the 1394 bus comprise a combination of CIPs, SPHS, and TSPs.
An isochronous packet in a cycle time n (corresponding to one cycle of isochronous transmission on the 1394 bus) shown in FIG. 2 comprises one CIP, one SPH, and one TSP. An isochronous packet in a cycle time n+1 shown in FIG. 2 comprises one CIP only.
An isochronous packet in a cycle time n+3 shown in FIG. 2 comprises one CIP, two SPHs, and two TSPs.
FIG. 3 of the accompanying drawings is a timing chart showing the timing of transmission of isochronous packets on the 1394 bus which are carried out corresponding to the isochronous packets shown in FIG. 2.
The isochronous packets transmitted in respective cycles of isochronous transmission on the 1394 bus may not necessarily have the same size. The transmission pattern representing the arrangement of isochronous packets is stored in a transmission pattern description memory area of the main memory 4.
The CPU 1 controls a 1394 DMA controller 5 to transmit isochronous packets stored in the main memory 4 over the 1394 bus based on the transmission pattern stored in the transmission pattern description memory area of the main memory 4.
The IDE controller 3 controls the recording of data in and the reading of data from the storage device 2, records data supplied from the CPU 1 or the 1394 DMA controller 5 in the storage device 2, and supplies data read from the storage device 2 to the CPU 1 or the main memory 4.
The main memory 4 has a transmission buffer area as well as the transmission pattern description memory area.
Based on a transmission pattern stored in the transmission pattern description memory area of the main memory 4, the 1394 DMA controller 5 reads, by way of DMA transfer, isochronous packets stored in the transmission buffer of the main memory 4 in synchronism with isochronous transmission cycles on the 1394 bus, and transmits the read isochronous packets over the 1394 bus.
A transmission process carried out by the CPU 1 will be described below with reference to a flowchart shown in FIG. 4 of the accompanying drawings.
In step S11, the CPU 1 controls the IDE controller 3 to read MPEG2-TS data from the storage device 2 into the transmission buffer of the main memory 4. The MPEG2-TS data, which is read into the transmission buffer of the main memory 4 are handled as isochronous packets.
In step S12, the CPU 1 checks the lengths of isochronous packets in the transmission buffer, and describes the lengths of isochronous packets to be transmitted in respective isochronous cycles in the transmission pattern description memory.
In step S13, the CPU 1 determines whether or not all the isochronous packets stored in the transmission buffer have been described. If it is determined that not all the isochronous packets stored in the transmission buffer have been described, then control goes back to step S12 to repeat the process of describing the lengths of the isochronous packets.
If all the isochronous packets stored in the transmission buffer have been described in step S13, then control goes to step S14. The CPU 1 instructs the 1394 DMA controller 5 to send the isochronous packets by means of isochronous transmission according to the data stored in the transmission pattern description memory. Then, the processing sequence shown in FIG. 4 is put to an end.
The process of describing the transmission pattern of all the isochronous packets requires a large memory capacity for storing the isochronous packets to be transmitted, and results in a large processing load for checking the lengths of the isochronous packets.